Nice article by Damon Wischik
1. Introduction
Today, the buffer size in core Internet routers is
typically chosen according to a rule of thumb which
says: provide at least one round trip time's worth of
buffering. The round trip time is often taken to be
around 250ms (it takes 134ms to send a packet half
way round the world and back, but queueing delay
may plausibly add 100ms). A 40Gb/s linecard
therefore needs 1.25GByte of memory.
Such large memories are hard to build in electronics.
(The problem is that data can arrive at line rate, so
the memory needs to be writeable at line rate. Such a
high memory bandwidth is hard to engineer—and
DRAM access speeds increases at only 7.5% a year
[6].) Such large memories are also wildly impractical
for any all-optical router that we can conceive of
today.
Recent theoretical work has challenged the rule of
thumb: it seems that a buffer of just 20 packets
should be sufficient. The modeling behind this deals
with TCP's algorithm for congestion control, with very
short-timescale traffic statistics, and with queueing
theory for Poisson traffic. (Long-range dependence
has no bearing on buffer size.) This article outlines
the theory.
Practical work has also challenged the rule of thumb.
A measurement study of a Sprint backbone router [1]
found that the queue size hardly ever exceeded 10
packets! (perhaps not surprising given that Sprint
aims to keep utilization below 20%). Preliminary
experiments on working routers [15] suggest that
buffers can be much smaller than they are now,
though the experimentation does not yet make clear
quite how much.
Small buffers have obvious practical benefits. In an
electronic router, the buffer could be on-chip, giving
much higher memory bandwidth. In an all-optical
router, 20-packet buffers might become feasible in the
coming few years.
more on the link
1. Introduction
Today, the buffer size in core Internet routers is
typically chosen according to a rule of thumb which
says: provide at least one round trip time's worth of
buffering. The round trip time is often taken to be
around 250ms (it takes 134ms to send a packet half
way round the world and back, but queueing delay
may plausibly add 100ms). A 40Gb/s linecard
therefore needs 1.25GByte of memory.
Such large memories are hard to build in electronics.
(The problem is that data can arrive at line rate, so
the memory needs to be writeable at line rate. Such a
high memory bandwidth is hard to engineer—and
DRAM access speeds increases at only 7.5% a year
[6].) Such large memories are also wildly impractical
for any all-optical router that we can conceive of
today.
Recent theoretical work has challenged the rule of
thumb: it seems that a buffer of just 20 packets
should be sufficient. The modeling behind this deals
with TCP's algorithm for congestion control, with very
short-timescale traffic statistics, and with queueing
theory for Poisson traffic. (Long-range dependence
has no bearing on buffer size.) This article outlines
the theory.
Practical work has also challenged the rule of thumb.
A measurement study of a Sprint backbone router [1]
found that the queue size hardly ever exceeded 10
packets! (perhaps not surprising given that Sprint
aims to keep utilization below 20%). Preliminary
experiments on working routers [15] suggest that
buffers can be much smaller than they are now,
though the experimentation does not yet make clear
quite how much.
Small buffers have obvious practical benefits. In an
electronic router, the buffer could be on-chip, giving
much higher memory bandwidth. In an all-optical
router, 20-packet buffers might become feasible in the
coming few years.
more on the link